IS = { zkontrolovano 04 Mar 2005 },
  UPDATE  = { 2004-10-08 },
  author =      {Milan Petr{\'\i}k},
  language =    {English},
  title =       {Design of Many-Valued Logical Circuits},
  year =        {2004},
  pages =       {97},
  school =      {Czech Technical University, 
                 Faculty of Electrical Engineering, 
                 Department of Cybernetics},
  address =     {Prague, Czech republic},
  month =       {February},
  day =         {16},
  figures =     {68},
  appendices =  {2},
  annote = { In this work we generalize the problem of logical circuit
    design to the many-valued logic with a finite number of logical
    values. We divide the problem to two main 

    In the first part we describe the design of disjunctive and
    conjunctive normal forms and, above all, their minimization using
    Svoboda maps. We also discuss the question of minimal functionally
    complete sets of operations and we find such a set containing two
    logical operations.
    In the second part we introduce many-valued memory circuits based
    on a generalization of the R-S memory circuit using gates
    implementing many-valued Sheffer, resp. Pierce, operation.
    In the appendix we introduce two programs relating to this
    topic. Program MVQuine expresses a many-valued logical function
    defined by a table of values in a disjunctive normal form based on
    the standard conjunction, the standard disjunction, Kronecker
    delta and all logical constants. Program MVSim is a simulator
    designed for demonstration which produces a time graph of the
    values of input, output and inner signals of a many-valued logical
    circuit.  The logical circuit is defined in a text file by a
    language designed for this purpose. },
  supervisor =  {Mirko Navara},
  keywords =    {fuzzy logic, many-valued logic, 
    sufficient set of logical connectives, optimized disjunctive normal forms, 
    optimized conjunctive normal forms, Svoboda maps, Veitch maps, 
    Marquand maps, Karnaugh maps, Quine-McCluskey algorithm, 
    fuzzy hardware, many-valued circuit design, many-valued flip-flop, 
    many-valued memory circuits},
  project =     {GACR 201/02/1540, CEEPUS SK-042},
  psurl =       {[PostScript, 2172 KB]},